microchip

Open 57d HybridNorth AmericaFull-timeStaff

Senior Technical Staff Engineer - Validation (System Design)

AI Automation C++ Ethernet Fiber +16 skills

Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.

70K – 143K $

Open 57d North AmericaFull-timeSenior

Senior Engineer I - Technical Support

Please follow the link to apply selecting "Microchip Recruiter" as your source: https://wd5.myworkdaysite.com/en-US/recruiting/microchiphr/External/job/Senior-Engineer-I---Technical-Support_R731-26 Job…

Assembly Salesforce

Open 57d North AmericaStaff

Sr Tech Staff Engineer - Design (Signal & Power Integrity)

Ansys FPGA Microcontrollers Oscilloscope SerDes +1 skills

Senior Technical Staff Engineer responsible for developing Signal and Power Integrity methodologies for high-speed FPGA products, running pre- and post-layout SIPI simulations, optimizing PDN and SerDes transceivers, and mentoring a global cross-functional team at Microchip in San Jose.

91K – 232K $

Manager - Product Marketing

Open 57d North America

Business Development FPGA Go-to-Market Microcontrollers

Please follow the link to apply selecting "Microchip Recruiter" as your source: https://wd5.myworkdaysite.com/en-US/recruiting/microchiphr/External/job/Manager---Product-Marketing_R3664-26 Job Description:…

Open 57d North AmericaSenior

Sr Client Engagement Manager

Please follow this link to apply (Select Microchip Recruiter) as your source: https://wd5.myworkdaysite.com/en-US/recruiting/microchiphr/External/job/Senior-Client-Engagement-Manager_R3273-26 Job Description: Microchip…

CRM Networking Tableau

Open 57d HybridNorth AmericaStaff

Technical Staff Engineer - Design (FPGA Fabric)

C++ FPGA Perl Python Verilog +1 skills

Design and optimize FPGA fabric architecture—interconnect, routing, logic elements, memory blocks, and clocking—at Microchip's FPGA Business Unit, using full-custom mixed-signal design, HDLs (Verilog/VHDL), and scripting on advanced process nodes.

88K – 232K $