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Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.
Senior Technical Staff Engineer responsible for developing Signal and Power Integrity methodologies for high-speed FPGA products, running pre- and post-layout SIPI simulations, optimizing PDN and SerDes transceivers, and mentoring a global cross-functional team at Microchip in San Jose.