OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.
(Staff/ Sr. Staff) Machine Learning Engineer
Lead research and development of ML algorithms and toolchains for Edge AI, focusing on quantization, compression, and on-device learning to optimize models for constrained hardware.
(Sr.) ISP RTL Design Manager
Leads a team to design and implement image signal processing (ISP) hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while collaborating with algorithm and system teams.
ISP RTL Design Engineer
Designs and verifies RTL implementations of image signal processing algorithms using Verilog/SystemVerilog/SystemC to optimize for power and gate count.
(Sr./Staff) ISP RTL Design Engineer
Design and implement image signal processing (ISP) algorithms into hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while verifying logic at ISP and system levels.
(Sr./Staff) NPU Design Engineer
Responsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and…
Design Verification Manager
Leads a team to verify complex SoC designs using UVM, C/C++ co-simulation, and formal methods, ensuring zero-defect delivery.
(Sr./Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them through simulation, and programs embedded C/assembly to meet power, timing, and area targets.
(Sr./Staff) ASIC Design Engineer
Designs and verifies RTL in Verilog/SystemVerilog for on-chip test and diagnostic IP, integrates it into SoCs, and collaborates with analog/mixed-signal teams to detect failures.
(Sr./Staff) Software Engineer, Edge AI - Toolchain
Builds and maintains the compiler toolchain that optimizes AI models for OMNIVISION’s Neural Processing Units, enabling customers to deploy models efficiently on edge devices.
(Staff/Sr. Staff) Software Engineer, Edge AI - Toolchain
Builds and maintains the compiler toolchain that optimizes AI models to run efficiently on the company’s neural processing units, collaborating with inference and application teams.
(Sr./Staff) Digital Design Verification Engineer
Design verification engineer building UVM/C++ verification flows for complex video-processing hardware to achieve zero-defect silicon.
(Staff/Sr. Staff) Digital Design Verification Engineer
Design verification engineer developing UVM, C/C++ co-simulation, and formal verification for complex digital designs to achieve zero-defect silicon.
(Sr. Staff/ Staff) NPU Design Lead/Engineer
Lead the microarchitecture and RTL design of a Neural Processing Unit (NPU) using Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with verification and software teams.
(Staff/Sr. Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them, and programs embedded C/assembly to meet power, timing, and area targets.