(1) SDC validation and perform STA (2) Advance STA signoff flow, domain knowledge enhancement (3) Timing closure with APR engineer (4) Review clock structure and Adjust clock tree for timing fixing
(1) Ongoing project R2G synthesis (top down/button up) (2) Logic equivalent check with R2G/G2G (3) Pre netlist timing closure (4) Synthesis flow maintenance
(1) Timing Closure Fixing (2) DFT expert (SCAN/ATPG/ MBIST/BSCAN/MBISR/At-Speed) (3) Hierarchical Experience is preferred for 100M+ gate count (4) CAD tool evaluation and consultant for frontend implementation
1. At least 5 years experience 2. Advanced process node capabilities, beyond 7nm(must) / more advanced processes are better 3. Well know about Voltus or Redhawk tools for IREM analysis 4. Link with Physical engineers…
(1) DFT planning & implementation for MBIST/SCAN/ATPG/BSCAN. (2) Perform STA & timing closure for DFT modes. (3) Create DFT test pattern & perform DFT Verilog simulation. (4) Co-work with Test Engineers to bring-up…
1. APR Implementation Floorplan、placement、clock tree synthesis Routing、timing optimization 2. Physical verification (DRC/LVS) 3. Timing Closure STA PT、Tweaker 4. Power analysis and fixing (IR/EM) 5. Low power…
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