Retym
Developing coherent DSP silicon for AI data center infrastructure.
Company facts
- Founded
- 2021
- Employees
- 150
- Headquarters
- United States
- Type
- Private
- Funding
- Series D · $182M · 2025
Open positions
Senior BackEnd (Physical design) Engineer
Leads full RTL-to-GDSII backend flow for semiconductor design, focusing on timing closure, low-power optimization, and physical implementation (floorplanning, CTS, IR-drop) while collaborating with design teams and external vendors.
System Integration Engineer
Hands-on system integration engineer at Retym (Ramat Gan, fully on-site) who brings up and validates PCBs, EVBs, and optical modules with customer platforms — debugging silicon-to-system issues, analyzing BER/signal integrity in the lab, and building Python/MATLAB test automation. Requires a B.Sc. in EE and 6+ years of hardware/system validation experience.
System Validation engineer
As System Validation engineer, you will play a crucial role in designing, testing, and troubleshooting Analog circuits within a laboratory setting. Your expertise in Analog electronics and proficiency in operating…
Analog Design Engineer
Designs high-end ADC/DAC circuits for optical communication in advanced semiconductor processes, focusing on analog/mixed-signal IC development and verification.
Production Test Engineer – High-Speed Mixed-Signal ICs
The Production Test Engineer will manage and optimize test processes for high-speed mixed-signal ICs in a high-volume manufacturing environment. The role involves using ATE platforms to ensure device quality, troubleshooting test failures, and collaborating with design teams to improve yield.
System Director Manager
Overview The System Director Manager for Optical Digital DSP base Systems is a senior leadership role responsible for managing and directing the development, implementation, and optimization within optical…
Senior Analog Design Engineer
A senior analog/mixed-signal IC engineer who designs and technically leads high-end ADC/DAC and related analog blocks (PLLs, SerDes) for optical communication, from architecture and specification through verification and tape-out in advanced FinFET/GAA process nodes.
VLSI Design Engineer
VLSI Design Engineer/Micro-architect responsible for designing cutting-edge communication systems from scratch using ASIC/FPGA with Verilog/SystemVerilog.
BackEnd (Physical design) Engineer
The Backend Physical Design Engineer will manage the full RTL-to-GDSII implementation flow, including synthesis, floorplanning, and timing closure for high-frequency, low-power designs. The role involves collaborating with design teams and external vendors to ensure successful tape-out and silicon performance.