Retym

Open 27d On-siteNorth AmericaC-level

9 hours ago

Optical DSP Chief Architect

Asic C++ Firmware MATLAB Python +1 skills

Leads DSP system architecture for high-speed optical transceivers (800G/1.6T+), optimizing algorithms like equalization and clock/data recovery while collaborating with hardware/photonics teams to design next-gen optical chips.

Open 27d On-siteNorth America

9 hours ago

VLSI Design Engineer

Ethernet Perl Python Rtl SystemVerilog +2 skills

VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.

Open 27d HybridMENA, North America

10 hours ago

Analog Design Engineer

Designs high-end ADC/DAC circuits for optical communication in advanced semiconductor processes, focusing on analog/mixed-signal IC development and verification.

11 hours ago

System Validation engineer

Open 27d On-siteMENA

Automation Fiber FPGA MATLAB Oscilloscope +4 skills

As System Validation engineer, you will play a crucial role in designing, testing, and troubleshooting Analog circuits within a laboratory setting. Your expertise in Analog electronics and proficiency in operating…

15 hours ago

Production Test Engineer – High-Speed Mixed-Signal ICs

Open 27d HybridMENA

Oscilloscope Process Improvement Test Automation

The Production Test Engineer will manage and optimize test processes for high-speed mixed-signal ICs in a high-volume manufacturing environment. The role involves using ATE platforms to ensure device quality, troubleshooting test failures, and collaborating with design teams to improve yield.

Open 27d On-siteNorth AmericaSenior

15 hours ago

Senior Embedded SW Engineer

API CI/CD Embedded Linux Embedded Software Firmware +9 skills

Senior Embedded SW Engineer builds and maintains DSP firmware from scratch, working across low-level, infrastructure, and application layers while collaborating with digital/analog engineers and international teams.

Open 27d On-siteCISJunior

15 hours ago

ASIC backend designer (Graduate)

Open 27d On-siteCIS

Armenia

Entry-level ASIC back-end (physical design) engineer joining Retym's silicon design team in Yerevan: a recent graduate works alongside senior engineers on block- and chip-level implementation using RTL2GDS flows (synthesis, floorplan, placement, CTS, routing) and timing closure on 2nm-and-below nodes. Core skills: VLSI/CMOS fundamentals, STA, Linux, Tcl.

Analog layout designer (Graduate)

Armenia

Entry-level analog layout engineer at Retym in Yerevan, working on high-end ADC/DAC chip layouts for optical communication in advanced TSMC process nodes. Day to day involves analog layout work using Mentor and Cadence tools with DRC/LVS/ERC flows.

Senior BackEnd (Physical design) Engineer

Open 27d HybridCIS, MENASenior

Leads full RTL-to-GDSII backend flow for semiconductor design, focusing on timing closure, low-power optimization, and physical implementation (floorplanning, CTS, IR-drop) while collaborating with design teams and external vendors.

Senior Analog Layout Designer

Open 27d On-siteCISSenior

Armenia

Designs high-performance ADC/DAC circuits in advanced TSMC processes for optical communication hardware, focusing on low-noise, high-speed analog layouts.

Open 27d On-siteNorth AmericaSenior

2 weeks ago

Senior Layout Designer

The Senior Layout Designer will develop high-end ADC/DAC circuits for optical communication using advanced sub-micro processes. The role requires extensive experience with Cadence layout tools and TSMC FinFET or Gate All Around technologies.

2 weeks ago

System Director Manager

Open 27d On-siteMENA

Assembly C++ Fiber MATLAB Oscilloscope +4 skills

Overview The System Director Manager for Optical Digital DSP base Systems is a senior leadership role responsible for managing and directing the development, implementation, and optimization within optical…

2 weeks ago

VLSI Design Engineer

Open 27d HybridMENA

Ethernet FPGA Perl Python Tcl +1 skills

VLSI Design Engineer/Micro-architect responsible for designing cutting-edge communication systems from scratch using ASIC/FPGA with Verilog/SystemVerilog.

3 weeks ago

BackEnd (Physical design) Engineer

Open 27d HybridMENA

Open 27d On-siteNorth America

The Backend Physical Design Engineer will manage the full RTL-to-GDSII implementation flow, including synthesis, floorplanning, and timing closure for high-frequency, low-power designs. The role involves collaborating with design teams and external vendors to ensure successful tape-out and silicon performance.

Engineering Site Manager – Semiconductor Startup

Asic C++ Firmware Performance Management Python +3 skills

About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…

Open 27d HybridMENASenior

4 weeks ago

Senior Analog Design Engineer

For an exciting well-funded start-up, we are looking for an excellent analog mixed signal engineer. You will develop high end ADC/DAC in advanced process for optical communication. Requirements Minimum Qualifications…

Open 27d RemoteNorth AmericaC-level

6 months ago

VP/Sr. Director of Marketing – Coherent DSP ASIC

Demand Generation Go-to-Market Lead Generation Sales Enablement

We are seeking a strategic and hands-on Vice President of Marketing to lead our marketing and product positioning efforts as we bring cutting-edge Coherent DSP ASIC solutions to market. This individual will define the…