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DV(Design Verification)工程師
APAC
Taiwan
Central and Western District, Tainan City1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of ASIC design flow. 5.…
Asic Perl Python Uvm Verilog
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數位IC驗證工程師(定期契約)
APAC
Taiwan
Central and Western District, Tainan City1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of ASIC design flow. 5.…
Asic Perl Python Uvm Verilog