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數位IC設計工程師3-4(台南)
APAC
Taiwan
Central and Western District, Tainan City(1) Familiar with the RTL design of TCON. (2) Familiar with verilog, logic synthesis and design flow.
Rtl Verilog
2 views 2 weeks ago
DV(Design Verification)工程師
APAC
Taiwan
Central and Western District, Tainan City1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of ASIC design flow. 5.…
Asic Perl Python Uvm Verilog
2 views 2 weeks ago
FPGA設計與合成-車用(台南)
APAC
Taiwan
Central and Western District, Tainan City1. FPGA驗證平台開發 2. FPGA timing constraint、synthesis and timing closure 3. Verilog Coding and Simulation 4. Xilinx ISE/Vivado, Altera Quartus II Implementation 其他工作條件限制: 1. 熟悉Xilinx及Altera FPGA 2. 熟悉I2C/SPI、eDP、iSP…
FPGA Verilog
1 views 2 weeks ago
數位IC驗證工程師(定期契約)
APAC
Taiwan
Central and Western District, Tainan City1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of ASIC design flow. 5.…
Asic Perl Python Uvm Verilog