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5 months ago
RTL Design Engineer - VHDL/Verilog
APAC
India
Job Description : - Requirements generation and RTL design using VHDL/Verilog. - FPGA development using Xilinx/Altera (Intel) FPGA platforms. - Perform synthesis, floorplanning, timing analysis, and timing closure…
Ethernet FPGA PCIe Rtl SerDes +2 skills