SignOff Semiconductors

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Lead Design Enginneer

Ethernet PCIe Stakeholder Management

Lead SoC Design Engineer in Bangalore working as an individual contributor driving chip-level integration for complex SoC programs: integrating IPs/subsystems, clocking/reset architecture, STA and timing closure, and signoff checks (Lint, CDC, synthesis). Requires 8-12 years in SoC design with protocols like PCIe, Ethernet, AXI, and SPI.

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Senior Physical Design Engineer

Malaysia

Senior Physical Design Engineer who owns the full RTL-to-GDSII flow for complex ASIC/SOC blocks: floorplanning, power planning, placement, CTS, routing, and signoff (timing, IR, EM, DRC/LVS). Work centers on PPA optimization and ECO closure using tools like Innovus, Tempus, Voltus, RedHawk, and Calibre.

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Senior Design Verification Engineer

Asic C++ Ethernet FPGA PCIe +6 skills

SignOff Semiconductors is hiring a Senior Design Verification Engineer in Bangalore to lead ASIC/SoC/IP verification projects for global semiconductor customers. The role involves defining verification plans, building UVM/SystemVerilog testbenches, and driving simulation, regression, debugging, and coverage closure.

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Lead Physical Design Engineer

Malaysia

Leads ASIC/SOC physical design from RTL to GDSII for complex sub-systems in Bayan Lepas, Malaysia — owning floorplanning, CTS, routing, and signoff (timing, IR, EM, DRC/LVS) with tools like Innovus, Tempus, Voltus, RedHawk, and Calibre, while driving PPA optimization, ECO closure, and mentoring junior engineers.

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Sr Manager / Director - Physical Design

Leadership role owning ASIC/SoC physical design and timing signoff at SignOff Semiconductors in Bangalore: building and mentoring physical design/CAD teams, driving full-chip implementation (floorplanning, placement, CTS, routing), and signoff closure (STA, IR/EM, DRC/LVS, UPF/CPF) using Synopsys/Cadence EDA tools. Requires 12-20 years' experience with 2+ years in senior management.

AI Automation CAD Rtl

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Design Engineer II – Memory Layout

Cadence Virtuoso Cmos Stakeholder Management

We are seeking a highly motivated Memory Layout Engineer with strong expertise in custom layout development for advanced memory compilers. The ideal candidate will have hands-on experience in SRAM/MRAM layout design,…