Lead Design Enginneer
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Summary
Lead SoC Design Engineer in Bangalore working as an individual contributor driving chip-level integration for complex SoC programs: integrating IPs/subsystems, clocking/reset architecture, STA and timing closure, and signoff checks (Lint, CDC, synthesis). Requires 8-12 years in SoC design with protocols like PCIe, Ethernet, AXI, and SPI.
Lead SoC Design Engineer
We are looking for an experienced SoC Design Engineer to work as an individual contributor, driving chip-level integration activities for complex SoC programs.
Key Responsibilities
- Perform chip-level integration of proprietary IPs and subsystems.
- Handle multiple SoC projects and drive integration activities independently.
- Work closely with SoC Integration Leads on clocking, reset architecture, and overall chip implementation.
- Develop and validate timing constraints, perform STA, and support timing closure.
- Execute signoff checks including Lint, CDC, and synthesis validation.
- Drive memory/IP integration and optimize memory selection for performance, area, and power.
- Collaborate with cross-functional teams across design, verification, DFT, and physical design.
Requirements
Required Skills & Experience
- 8-12 years of experience in SoC design and chip integration.
- Strong hands-on experience in large-scale SoC integration.
- Good understanding of industry-standard protocols such as PCIe, Ethernet, AXI, and SPI.
- Expertise in STA, synthesis, timing closure, clock/reset methodology, Lint, and CDC signoff.
- Experience with full-chip implementation and integration flows.
- Strong debugging, problem-solving, and stakeholder management skills.
Preferred Profile
- Self-driven individual contributor capable of owning end-to-end integration activities.
- Experience working on complex, high-performance SoCs from integration through signoff.
- Ability to manage multiple priorities and deliver in a fast-paced development environment.