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Six-month, full-time internship in San Jose on SK hynix's SoC design team building SSD controllers for enterprise and AI data centers. The intern writes RTL in Verilog/SystemVerilog for IP modules and documents/collaborates with verification, silicon validation, and firmware teams.
Sr. Staff/Principal engineer leading advanced-node (7nm/5nm/3nm) SoC physical design from synthesis through GDS for SK hynix's memory SoCs — owning P&R, timing closure with PrimeTime, physical verification with Calibre, and power integrity with RedHawk, while mentoring engineers and building design flows in Tcl/Perl/Python.
Sr. Staff Physical Design Engineer at SK hynix memory solutions in San Jose, leading SoC physical implementation from RTL to GDS on advanced nodes (7nm/5nm/3nm). Day-to-day work spans synthesis, place-and-route, CTS, timing closure with PrimeTime, physical verification with Calibre, and power integrity with RedHawk, plus mentoring and flow automation.
Senior signal/power integrity engineer developing next-generation SSD products at SK Hynix Memory Solution: designs and simulates high-speed interfaces (PCIe Gen4/5/6, DDR4/5, ONFI NAND), guides SoC package and PCB design, and validates designs in the lab with oscilloscopes, VNA, and TDR while mentoring engineers and debugging issues across development stages.
Signal/Power Integrity Engineer developing next-generation SSD products at SK Hynix Memory Solution. Day to day: provide SI/PI expertise for SSD controller (SoC) substrate and PCB design, run pre/post-layout simulations with tools like Sigrity, HFSS, ADS and HSPICE, and validate designs in the lab using oscilloscopes, VNA and TDR across PCIe Gen4/5/6 and DDR4/5 interfaces.
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