ASIC Design Intern
Summary
Six-month, full-time internship in San Jose on SK hynix's SoC design team building SSD controllers for enterprise and AI data centers. The intern writes RTL in Verilog/SystemVerilog for IP modules and documents/collaborates with verification, silicon validation, and firmware teams.
About the Company:
At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
Internship Duration: 6 months
Hours: 40 hours per week
Start Date: Immediately (November 2026/December 2026)
Location: San Jose
About The Role
You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.
Responsibilities
- RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
- Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.
Minimum Qualifications
- Education: Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
- Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
Preferred Qualifications
- Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
- Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR)
- Scripting skills (Python, Perl, TCL) and Linux command-line experiences
- Strong problem-solving and communication skills
- Proficiency in AI tool to generate synthesizable and functional RTL code
COMPENSATION: $35/hr - $45/hr
Skills
As published by greenhouse · 10 questions · 2 written answers
Basics
First Name, Last Name, Email, Phone, Resume/CV, Cover Letter
Short answers (5)
- Preferred First Name optional
- LinkedIn Profile optional
- Website optional
- Can you complete a 6 month internship starting immediately?
- Where are you currently located?
Pick from a list (3)
- This role requires you to work onsite 5 days a week at our San Jose location. Is that a requirement you can meet?
- Will you now or in the future require sponsorship to work in the U.S.?
- If you are not located in San Jose, CA are you willing to relocate?
Written answers (2)
- When do you graduate? If you have not graduated yet, how do plan to work 40 hours for this internship?
- What is your current work authorization?