SVENTL ASIA PACIFIC PTE. LTD.

Physical Design Engineer

Open 94d APAC

The Physical Design Engineer is responsible for the end-to-end implementation of chip designs, from netlist to GDSII, including floor planning, timing signoff, and clock tree synthesis. The role requires expertise in industry-standard EDA tools like Synopsys ICC/ICC2 or Cadence Innovus and experience with advanced process nodes.

Tcl

ATE Test Engineer

Open 43d APAC

ATE Test Engineer responsible for preparing production and qualification test packages (hardware/software) for CMOS ICs, ensuring transfer to test sites, and supporting debug/buyoff, primarily using Advantest V93k or J750 platforms.

Cmos C++ Java Python VBA

Design Verification Engineer

Open 43d APAC

Asic Ethernet Perl Rtl Tcl +2 skills

The Design Verification Engineer will develop verification environments, test plans, and perform functional RTL testing at the IP and SoC levels. The role requires expertise in ASIC verification methodologies, SystemVerilog, and various communication protocols.

Senior Validation engineer

Open 43d APACSenior

Automation C++ Ethernet Firmware JTAG +3 skills

Responsibilities/Job Scope: • Pre-silicon verification and post-silicon system validation • Test case and test automation scripts development and test plan execution • Debug system (hardware, software and firmware),…