Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
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IC設計類:IP Design Verification Engineer (熟悉UVM/SystemVerilog)
APAC
Taiwan
Zhubei City, Hsinchu County***請將英文履歷投遞到以下連結:https://careers.synopsys.com/job/hsinchu/asic-design-verification-engineer-principal/44408/100703928160*** You Are: You are a highly skilled and experienced verification engineer, passionate about…
Bash C++ Embedded Software Ethernet Firmware +7 skills