IC設計類:IP Design Verification Engineer (熟悉UVM/SystemVerilog)

***請將英文履歷投遞到以下連結:https://careers.synopsys.com/job/hsinchu/asic-design-verification-engineer-principal/44408/100703928160***

You Are:
You are a highly skilled and experienced verification engineer, passionate about delivering high-quality solutions for advanced memory and interface technologies. With over a decade of hands-on expertise, you thrive in the fast-paced world of ASIC/SoC verification, tackling challenges associated with state-of-the-art DDR (DDR5, LPDDR6) and HBM IP. Your deep technical knowledge spans UVM-based methodologies, constraint random verification, and formal verification techniques, enabling you to develop robust verification environments from the ground up.
You are proactive, self-motivated, and a natural problem-solver who excels under tight deadlines and dynamic requirements. Your communication skills allow you to collaborate effectively across multidisciplinary teams and mentor junior engineers. You’re comfortable leading and coordinating design reviews, debugging complex RTL issues, and ensuring full functional coverage from specification to silicon. You bring strong scripting and programming skills, adaptability to evolving technologies, and a genuine commitment to innovation, quality, and teamwork. Above all, you value diversity, equity, and inclusion, and you’re eager to make a tangible impact within a world-class organization.

What You’ll Be Doing:

• Leading edge IP verification for DDR (DDR5, LPDDR6) controller and HBM interface technologies.
• Studying and interpreting JEDEC and related standard specifications to ensure compliance and performance.
• Developing and implementing advanced verification strategies, plans, and testbench architectures using UVM/VMM/OVM methodologies.
• Building infrastructure, coverage models, and checkers, and analyzing/debugging regression failures to achieve comprehensive functional coverage.
• Collaborating with design teams to debug and resolve RTL issues and working with VIP teams to address verification IP concerns.
• Providing metric-driven reports on verification progress and managing deliverables to meet project schedules.
• Mentoring junior engineers and acting as a technical expert, fostering knowledge sharing and continuous improvement within the team.
• Leading and coordinating design review meetings, ensuring high standards and successful project outcomes.

The Impact You Will Have:

• Delivering high-quality, silicon-proven DDR and HBM IP that powers next-generation SoCs and systems.
• Accelerating time-to-market for industry-leading products by ensuring robust, scalable, and fully verified controller IP.
• Driving innovation by implementing best-in-class verification methodologies and promoting a culture of technical excellence.
• Enhancing collaboration and cross-functional knowledge sharing across global design and verification teams.
• Mentoring and developing junior engineers, strengthening the technical foundation of the organization.
• Supporting customers and internal teams, ensuring seamless adoption of IP and successful product releases.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering or related field (BSEE/MSEE preferred).
• 10–15+ years of hands-on experience in ASIC/SoC verification, with expertise in UVM-based methodology and SystemVerilog.
• Proficiency in developing testbenches, constraint random verification, coverage closure, and failure analysis.
• Experience interpreting and applying JEDEC and interface protocol specifications (DDR, HBM, PCIe, AMBA, AXI, CHI, SD, eMMC, Ethernet, USB, MIPI).
• Strong scripting skills in Shell, Perl, Python, and TCL; experience with C/C++ and firmware/embedded software is a plus.
• Familiarity with formal verification techniques, assertions, and functional safety standards (e.g., ISO26262, FMEDA) is advantageous.
• Experience working in Unix environments and with industry-standard simulation tools.