Founding-hire physical design engineer at a startup building energy-efficient AI silicon. Day to day, you own RTL-to-GDSII implementation of complex blocks and SoC top level — floorplanning, CTS, routing, PPA optimization, and sign-off (STA, IR drop, EM, DRC/LVS) — plus flow automation with EDA tools like Synopsys Fusion Compiler and Cadence Innovus.
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