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Role Overview We are looking for a CAD Back-end Lead to build, integrate, and support the design flows used by Velaura’s Custom Design and Physical Design teams. This role will own the CAD framework supporting custom…
Leads system-level design verification for Velaura's Physical AI SoC, owning the verification plan from RTL blocks through sign-off and tape-out while building and directing a small team of verification engineers. Hands-on work centers on SystemVerilog/UVM and C/C++, covering boot/root of trust, clock/reset, low power, and IO/memory subsystems.
Design Verification Engineer verifying Velaura's next-generation Physical AI SoC at the system level — covering boot/root of trust, clock/reset, low power, and IO/memory subsystems through sign-off and tape-out. Core stack includes SystemVerilog/UVM, C/C++, ARM/RISC-V SoC simulation flows, CDC/RDC analysis, and UPF low-power verification.
Senior CAD engineer who owns pre-silicon front-end automation at a custom silicon startup: RTL design flows, DV simulation/regression flows, emulation and FPGA prototyping, keeping those flows reliable from RTL entry through DFT handoff. Core tech: SystemVerilog, Python, Linux/LSF/Slurm, Synopsys/Cadence/Siemens EDA tools, plus AI-assisted tooling.
Senior IT leader who owns infrastructure and operations end to end: hybrid cloud/on-prem compute for compute-intensive EDA workloads, HPC scheduling and storage, CI/CD, and the security program protecting design IP (IAM, endpoint, SOC 2 readiness). Hands-on with Linux, Azure/GCP/AWS, Kubernetes, and enterprise networking while leading and growing the IT team.
Own verification of custom AI accelerator hardware for matrix/vector compute engines, ensuring numerical correctness and performance under LLM workloads using SystemVerilog/UVM and reference models.
Designs and executes verification plans for a custom Physical AI SoC’s CPU, ensuring correctness, performance, and reliability of microarchitecture components (fetch/decode/cache) via SystemVerilog/UVM/C++ testbenches and real-world workload testing.
Principal architect role defining and leading the AI SoC runtime that coordinates sensor ingest, AI inference, and postprocessing across heterogeneous compute engines for edge/robotics applications.
Own the end-to-end SoC program for a next-gen Physical AI chip, coordinating silicon, platform, software, and vendor teams from architecture through tapeout and bring-up.
Administer and secure Linux servers, cloud infrastructure, networking, and endpoints while providing Tier 2/3 IT support in a fast-paced AI startup.
Role Overview Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where energy is scarce, thermal headroom is limited, and every…
Role Overview Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where a fault in the chip can translate directly into unsafe…
Role Overview Velaura is designing the compute silicon that will power the next generation of robots, autonomous systems, and intelligent machines operating in the physical world. As Security Architect for our Physical…
Role Overview As a Sr. Staff/Principal Custom Circuit Design Engineer at Velaura AI, you will lead the architecture, design, and optimization of high-performance, low-power standard cell libraries and custom digital…
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing…
Role Overview As a Staff/Sr. Staff/Principal Physical Design Engineer at Velaura AI, you will be responsible for driving the physical implementation and sign-off of critical blocks for next-generation AI and…
Role Overview We are looking for an AI Systems Architect who sits at the intersection of machine learning models and hardware architecture. In this role, you will work across model development, algorithms, and hardware…
Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software…
Role Overview We are looking for a Performance Modeling Architect who will develop the modeling and simulation frameworks used to guide architectural decisions across our platform. In this role, you will build models…
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