AI/Deep learning Accelerator - IP Verification Engineer

About AnDLA

Andes Deep Learning Accelerator (AnDLA) is a highly efficient, cost-effective AI solution for edge devices and endpoints. AnDLA has hardwired processing units for matrix multiplication, convolution, pooling, and more functions on the roadmap.

About the Role

As a Verification Engineer on the AnDLA team, you will ensure the functional correctness of the AnDLA IP from specification to silicon-ready delivery. You will develop test plans and test patterns across multiple verification environments, from block-level self-checking UVM testbenches to system-level verification with AndesCore™ processors. You will also take part in FPGA synthesis and prototyping, which extends verification into real hardware. You will drive improvements to the verification flow and infrastructure, so the team can verify faster and more reliably. You will join AnDLA specification and micro-architecture discussions and work closely with design engineers.

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Responsibilities
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• Verify the AnDLA IP at block, subsystem, and system levels.
• Develop test plans and test patterns in C/C++ and SystemVerilog.
• Define, collect, and analyze code and functional coverage to drive verification closure.
• Build and maintain verification environments, including self-checking UVM testbenches and system-level environments with AndesCore processors.
• Perform FPGA synthesis and run FPGA-based validation, and debug issues found on the FPGA platform.
• Improve the verification flow and infrastructure, such as regression systems, automation scripts, and CI integration, to raise efficiency and quality.
• Take part in AnDLA specification and micro-architecture reviews, and work with design engineers to find and resolve issues early.