ASIC Design Verification Engineer
Posted Updated
Summary
Meta is hiring an ASIC Design Verification Engineer in Sunnyvale to verify IP and SoC designs for its data center hardware. Day to day, you'll own verification closure for a design module or sub-system: test planning, building UVM testbenches, and using simulation, formal, and emulation alongside ASIC, software, and post-silicon teams.
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.
As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
