ASIC Formal Verification Engineer, TPU Compute

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
• Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
• Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
• Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
• Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience in silicon development or ASIC/SoC design.
• Experience with SystemVerilog Assertions (SVA) and formal verification methods.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal).
• Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking.
• Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers.
• Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA).