AU-【板橋/竹北】知名外商科技業公司-Hardware DFT Engineer (年薪2M+/英文精通/歡迎2-8年經驗投遞！！！)

DFT Engineer - Scan / MBIST / ATPG
工作內容
Role Summary

• Design for Testability (DFT) Engineer to architect, implement, and verify advanced test structures (Scan, MBIST) to maximize silicon test coverage and guarantee high manufacturing yield. Key Responsibilities
• Implementation: Insert, integrate, and verify Scan chains, Memory BIST (MBIST), and test control logic into cutting-edge ASIC designs. ◦ Pattern Generation: Generate and simulate ATPG (Automated Test Pattern Generation) vectors, conducting rigorous low-power checks during test mode to prevent silicon damage.

Requirements & Qualifications

• 2+ years of experience in DFT insertion, ATPG pattern generation, and timing simulation closure.
• Deep knowledge of scan compression architectures, fault modeling (Stuck-at, Transition, Cell-aware), and memory testing.
• Familiarity with DFT EDA tools (e.g., Synopsys Tessent or Cadence Modus) and hardware description languages (Verilog/SystemVerilog).