Backend Engineer - DFT & RTL-to-Gate Design
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Summary
Hardware/physical design engineer at Amlogic (Singapore) implementing DFT and RTL-to-gate synthesis for complex chips: creating SDC constraints, running ATPG/MBIST test tasks, and driving timing and power closure in collaboration with RTL, PnR, and FE/BE teams.
AMLOGIC SINGAPORE PRIVATE LIMITED is seeking a hardware design professional to drive RTL-to-gate synthesis and DFT implementation for complex chips. You will collaborate with RTL, PnR, and FE/BE teams to ensure timing and power integrity across DFT designs.
Responsibilities include SDC creation, DFT tasks including ATPG/MBIST, and coordinating with cross-functional teams to achieve timing closure and robust testing.