AMLOGIC SINGAPORE PRIVATE LIMITED

Amlogic Singapore is hiring a senior physical design engineer to drive Place & Route on advanced process nodes, handling end-to-end backend flows from netlist to GDSII. The role involves collaborating with front-end teams on floorplan, clock, and power, and developing automated PD methodologies.

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last week

Senior Backend (Physical Design) Engineer

Open 47d APACSenior

Singapore

Responsible for backend physical design tasks from Netlist to GDSII including P&R, formal verification, static timing analysis, and tape-out, while collaborating on chip floorplan and powerplan and researching advanced process node methodologies.

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AMLOGIC SINGAPORE PRIVATE LIMITED

2 weeks ago

Backend Engineer - DFT & RTL-to-Gate Design

APAC

Singapore

Hardware/physical design engineer at Amlogic (Singapore) implementing DFT and RTL-to-gate synthesis for complex chips: creating SDC constraints, running ATPG/MBIST test tasks, and driving timing and power closure in collaboration with RTL, PnR, and FE/BE teams.

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amlogic singapore private limited

2 weeks ago

Backend Engineer Synthesis/DFT/STA

APACFull-time

Singapore

Backend IC design engineer at Amlogic (Jurong East, Singapore) doing RTL-to-gate synthesis, SDC constraints, Design-for-Test (scan insertion, ATPG, MBIST, boundary scan), and STA/timing closure for advanced SoC development, working with Synopsys EDA tools alongside physical design teams.

Perl Python Rtl Tcl Verilog

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amlogic singapore private limited

2 weeks ago

Backend Engineer Synthesis

APAC

Singapore

ASIC backend engineer at Amlogic Singapore performing RTL-to-gate-level logic synthesis, SDC creation, and DFT work (scan insertion, ATPG, MBIST, boundary scan) for digital chips. Collaborates with RTL, PnR, and test teams using EDA tools (DC/FC/TetraMax) plus Verilog, TCL, Perl, and Python to close timing and improve PPA.

Perl Python Rtl Tcl Verilog

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AMLOGIC SINGAPORE PRIVATE LIMITED

2 weeks ago

Backend Engineer – Synthesis

APAC

Singapore

Job Responsibilities - Responsible for synthesis from RTL to gate-level netlist - Work with RTL design team to create and verify SDC - Work with PnR engineers to improve PPA of digital modules - Responsible for the DFT…

Perl Python Rtl Tcl Verilog

Apply

Senior Physical Design Backend Engineer

Senior Backend (Physical Design) Engineer

Backend Engineer - DFT & RTL-to-Gate Design

Backend Engineer Synthesis/DFT/STA

Backend Engineer Synthesis

Backend Engineer – Synthesis

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