CAD / Design Enablement Engineer

About the role
We are a lean, fast-moving IC design house, and the design teams move only as fast as the flows and design kits underneath them. As our CAD / Design Enablement Engineer, you own the EDA environment end to end and serve as our primary point of contact to foundries and IP vendors. You are the person who makes sure every PDK, design kit, IP deliverable, and tool flow is in place, qualified, and working before the designers need it.

This is a high-ownership role with broad scope. You will touch everything from license servers to sign-off flows, and you will represent the company in regular conversations with foundry customer engineers (CE) and third-party IP suppliers. If you like being the connective tissue between vendors, tools, and design teams, this role is for you.

What you'll do
Vendor & foundry interface (a core part of this role)

• Act as the primary contact window to foundry customer engineers (CE) and third-party IP suppliers.
• Initiate and manage regular outreach to download, track, and stage PDKs, design kits, reference flows, and IP deliverables (digital/analog IP, memory compilers, I/O, standard cells, etc.).
• Maintain access credentials and entitlements on foundry and IP-vendor portals; manage NDAs, deliverable revisions, and release notes.
• Track design-kit and IP versions, flag updates and ECNs, and coordinate qualification before rollout to the design teams.
• Open, drive, and close tickets/cases with foundries and vendors; escalate and follow up until resolved.

EDA flow & environment ownership

• Install, configure, and qualify PDKs and design kits across the toolchain (Synopsys, Cadence, Siemens EDA, etc.).
• Build and maintain flows for synthesis, place & route, STA, DRC/LVS, and other sign-off steps.
• Develop and maintain automation and scripting (TCL, Python, Perl, Make, shell) to streamline setup, regression, and reporting.
• Manage the compute environment: license servers (FlexLM/license daemons), job scheduling (LSF/Slurm/SGE), storage, and version control.
• Maintain regression and CI infrastructure for flow and design-kit qualification.

Support & enablement

• Be the first line of support for designers on tool, flow, PDK, and IP issues.
• Document setups, flow usage, and onboarding so the team can self-serve.
• Continuously improve turnaround time, reproducibility, and reliability of the design environment.

What we're looking for

• BS/MS in Electrical/Computer Engineering or equivalent practical experience.
• Solid understanding of the IC design and sign-off flow (RTL-to-GDS or analog/custom flow) and where PDKs and IP fit in.
• Hands-on experience with EDA tools from at least one major vendor (Synopsys / Cadence / Siemens EDA).
• Experience working directly with foundry PDKs and third-party IP deliverables — installing, qualifying, and version-managing them.
• Strong scripting skills (Python and/or TCL, plus shell).
• Comfort administering Linux compute environments, license servers, and job schedulers.
• Excellent communication and follow-through — you will be the face of the company to external CEs and vendors, so you need to be organized, responsive, and proactive.

Nice to have

• Prior experience as a foundry/IP point of contact or in a CAD/Design Enablement role.
• Familiarity with multiple foundries (e.g., TSMC, Samsung, GlobalFoundries, UMC) and their portals/deliverable formats.
• Exposure to DFT, CDC/RDC, or other methodology areas.
• Startup or small-team experience — comfortable wearing multiple hats and setting up processes from scratch.

Why join us

• Broad ownership and direct impact — your work unblocks every design team.
• Direct relationships with foundries and IP partners; you'll be in the room (or the email thread) that matters.
• A small team where good ideas ship fast and you're not buried under process.