<Data Center> Datacenter Compute SoC Performance Modeling Architect

Role Summary
We are looking for a highly skilled Datacenter Compute SoC Performance Modeling Engineer. In this role, you will be at the forefront of defining our next-generation cloud and datacenter processors. You will develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs, identify performance bottlenecks, and project system performance across a wide range of datacenter workloads.
You will collaborate closely with CPU/Compute core architects, SoC architects, IP architects, workload characterization teams, and RTL designers to ensure our silicon delivers industry-leading performance-per-watt and scales efficiently to meet the demands of modern hyper-scale infrastructure.

Key Responsibilities

• Simulator Development: Design, develop, and maintain cycle-accurate and transaction-level performance models (C++/SystemC) for multi-core datacenter SoCs, including CPU cores, memory subsystems, interconnects (NoC), and high-speed I/O (PCIe/CXL).
• Workload Analysis & Profiling: Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines to drive architectural requirements.
• Performance Exploration: Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts.
• Bottleneck Identification: Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions.
• RTL & Silicon Correlation: Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon, ensuring model accuracy.
• Tooling & Infrastructure: Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis libraries.

#LI-JK1

• Education: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• Experience: 5+ years of industry experience in CPU, compute core, SoC, or system-level performance modeling and architectural analysis.
• Datacenter Focus: Experience profiling and analyzing hyperscaler workloads (e.g., SPEC CPU, cloud microservices, big data analytics, virtualization).
• Programming Skills:

-Expert-level proficiency in modern C++ (C++14/17 or later) and object-oriented design.
-Strong scripting skills in Python or Perl for data analysis and automation.

• Computer Architecture:

-Deep understanding of high-performance CPU microarchitecture (out-of-order execution, branch prediction, etc.) or computation engines (like PE array, Graph based compute, …)
-Comprehensive knowledge of memory hierarchies, cache coherency protocols (e.g., MESI, MOESI), and main memory technologies (DDR & LPDDR5/6, HBM).
-Familiarity with on-chip interconnects (e.g., AMBA CHI, AXI), I/O protocols (PCIe/CXL) and multiple-die architecture (e.g., UCIe)

• Modeling Frameworks: Hands-on experience with industry-standard simulators (e.g., gem5, Sniper) or building proprietary trace-driven/execution-driven simulators from scratch.
• Communication: Ability to clearly present complex performance data and architectural trade-offs to cross-functional teams and leadership.