<Data center>Digital IC Design/Integration Engineer/Manager_HsinChu/Taipei

1. Digital IP design (RTL design/Synthesis/integration/verification)
2. SoC Chip design/integration
3. DFT related design/plan/integration
4. STA Timing Closure Signoff
5. Design Flow development and enhancement.
6. Location: Taipei/HsinChu

Requirements

1. Familiar with SoC chip design flow
2. Experience in FE/BE integrating EDA tools and implementation experience.
3. Good at cross-department communication and coordination
4. Willing to think about process or architecture improvements
5. Experience in DFT test planning or STA timing sign-off is preferred
Education: Master's Degree