<Data Center>Serdes Digital IC Design Engineer

Design the Serdes high speed connection PHY architecture which targets at data center and AI products. The role of this position is to design and deliver the ASIC products to world class customer. You will contribute and build a Serdes PHY design which has low power, cost-effective, and high-speed performance. You can expand your view of the world and co-work with colleagues in multiple countries. The domain knowledge of this position includes digital communication design (EQ, FIR), analog macro design (PLL, ADC/DAC, Calibration), and SoC design (micro controller, bus protocol).

Requirements

Job Skills & Qualification:
–_x0001_Master degree in Electrical Engineering, Electronic Engineering, and Communication Engineering.
–_x0001_Knowledge of digital IC design flow including RTL coding, synthesis, setup/hold time analysis, clock tree, and DFT scan/mbist flow.
–_x0001_Knowledge of low power RTL design, dynamic/leakage power, power/clock gating, DVFS, IR drop, and voltage bin.
–_x0001_Experience in using EDA tool (lint, cdc, synthesis, cts, ptpx, etc.)
–_x0001_Knowledge of digital communication design such as EQ, FIR, MLSD, etc.
–_x0001_Knowledge of analog macro design such as PLL, ADC, DAC Calibration, etc.
–_x0001_Knowledge of processor system, including instruction pipeline, cache access, interrupt, boot flow and debug scheme.

Preferred Qualification:
–_x0001_Knowledge of Serdes and Ethernet standard (IEEE 802.3)
–_x0001_Knowledge of foundry technology node, package design, and silicon testing flow.
–_x0001_Knowledge of PAR flow, including floorplan, routing, LVS, DRC, and IR drop.
–_x0001_Good communication skill.
–_x0001_Ability to identify issue and present in a clear way.
Education: Master's Degree