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MediaTek 聯發科技

<Data center>TOP Designer & FE Integrator

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Description

1. Top design for testing: uArch, design, simulation:
- DFT top, PAD top

2. Top/sensor FE integration and simulation:
- eFUSE
- PVT sensor, aging sensor
- IO integration based on customer requirement

3. Test sequence preparation for Post-Si test and HTOL
4. RFI/RFQ: Sync customer testing structure, IO and sensor requirement

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