Design Technology Engineer

Dual responsibilities for design infrastructure setup:
1. Foundry technology
a) Establish SOC design infrastructure, including PDK integration, reference flows, SC, IO, Memory Compliers, IPs, design rule decks, to ensure seamless SOC team and customer adoption.
b) Cell library characterization and maintenance, i.e. generating Liberty (.lib) files with NLDM/CCS/ECSM timing, power, noise, and variation models.
c) Collaborate with manufacturing and SOC design teams to identify and resolve technical issues related to foundry process.
d) Perform in-depth analysis and benchmarking of advanced process technologies with EDA tools, including HSPICE/Spectre , Design Compiler (DC), and PrimeTime (PT) for PPA assessment.
e) Execute transistor-level SPICE simulations for critical path timing analysis, corner case validation (PVT, RC corners), and post-layout timing correlation.

2. EDA & IP
a) Installation, configuration, troubleshooting, and continuous improvement of EDA tool suites (Cadence, Synopsys, Siemens/Mentor) across design and verification environments.
b) Design process monitor and silicon-verification IP blocks for testchips to support process characterization, yield learning, and model calibration.

Education:
Bachelor and above degree majors in Micro-Electronics or E&E related field.

Professional Knowledge:

• With fundamental knowledge for Semiconductor and Integrated Circuits.
• Better with skills as following

o Proficiency with SPICE-level simulation tools (HSPICE, Spectre, FineSim)
o Expertise in Synopsys PrimeTime (PT) and Design Compiler (DC) for timing power analysis.
o Experience with standard cell re-characterization flows. Understanding of Liberty format (NLDM, CCS, ECSM), variation-aware modeling (OCV, AOCV, POCV, LVF), and library QA/validation flows.
o Familiar with foundry PDK deployment, SOC design methodologies, and customer-facing technical support.
o Proficiency in scripting languages (Python, Perl, TCL) for automation of characterization, data analysis, and infrastructure tasks.

Preferred Qualifications

• Direct experience supporting TSMC, GlobalFoundries, or similar leading foundry technologies.
• Knowledge of advanced node challenges (FinFET/GAA, backside power delivery, high-NA EUV, etc.).
• Background in silicon bring-up, testchip design, or process monitor/IP characterization.

Other Special Requirement:

• Excellent problem-solving skills with the ability to work across multi-functional, international teams in a fast-paced environment.
• Well English communication skills (written and verbal) for customer interaction and technical documentation.