Design Verification Engineer AI Accelerator
Posted Updated
Summary
Owns verification of custom AI accelerator hardware (matrix and vector compute engines): builds SystemVerilog/UVM test and coverage environments, develops C/C++/Python reference models for GEMM/GEMV, verifies numerical precision and performance, and supports emulation and pre-silicon bring-up.
You will own verification of custom AI acceleration units, including matrix and vector compute engines. You will build test and coverage plans, develop reference models, verify numerical behavior and data flow, evaluate performance, and support emulation and pre-silicon bring-up.
Responsibilities
- Own verification of custom AI acceleration units
- Create detailed test and coverage plans for numerical hardware
- Build verification environments using SystemVerilog, UVM, C, and C++
- Develop GEMM and GEMV reference models and compare hardware results
- Verify accelerator data flow, operand staging, tiling, accumulation, and writeback
- Verify precision, rounding, and quantization behavior
- Verify throughput, latency, utilization, and performance per watt
- Execute regressions and track bug and coverage metrics
- Support emulation and pre-silicon bring-up with compiler and runtime teams
Requirements
- 8 or more years verifying high-performance compute or complex digital designs
- LLM architecture and inference data flow
- GEMM and GEMV operations
- SystemVerilog
- UVM
- C
- C++
- Assertions
- Coverage-driven verification
- Reference models in C, C++, or Python
- FP16
- BF16
- FP8
- INT8
- Verification ownership from test plan through coverage closure
Benefits
- Competitive equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements