Design Verification Engineer CPU
Posted Updated
Summary
Verification engineer for a custom CPU: owns functional verification from test planning through coverage closure — building SystemVerilog/UVM environments, writing C/C++ instruction-level stimulus, verifying memory ordering, coherence, and performance, and supporting emulation, FPGA prototyping, and pre-silicon software bring-up.
You will own verification for functional domains of a custom CPU, from test planning through coverage closure. You will build verification environments, develop instruction-level stimulus, validate CPU behavior and performance, run regressions, and support emulation, FPGA prototyping, and software bring-up.
Responsibilities
- Own verification of CPU fetch, decode, load-store, and cache units
- Create detailed test and coverage plans with CPU and SoC architects
- Build verification environments using SystemVerilog, UVM, C, and C++
- Develop instruction-level stimulus and compare results with a golden instruction set simulator
- Verify memory ordering, coherence, exceptions, and privilege behavior
- Verify latency, bandwidth, and cache behavior
- Execute regressions and track bug and coverage metrics
- Support emulation, FPGA prototyping, and pre-silicon software bring-up
- Drive root-cause analysis across hardware and software boundaries
Requirements
- 8 or more years verifying high-performance CPUs or complex digital designs
- Computer architecture and microarchitecture
- SystemVerilog
- UVM
- C
- C++
- Assertions
- Coverage-driven verification
- Test planning
- Portable testbenches
- Transactors
- Hardware/software debugging
Benefits
- Competitive equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements