Design Verification Engineer – CPU
Summary
Own pre-silicon verification of custom CPU units (fetch, decode, load-store, caches) by building SystemVerilog/UVM environments, developing instruction-level stimulus, running regressions, and supporting FPGA/emulation bring-up.
You will own verification for custom CPU units such as instruction fetch, decode, load-store logic, and multiple cache levels. You will create test and coverage plans, build portable verification environments, develop instruction-level stimulus, compare results with a golden instruction set simulator, verify architectural behavior, execute regressions, and support emulation, FPGA prototyping, and pre-silicon software bring-up.
Responsibilities
- Own verification of custom CPU units including instruction fetch decode load-store logic and caches
- Translate microarchitecture intent into detailed test and coverage plans
- Build portable SystemVerilog and UVM verification environments with stimulus checkers assertions trackers and coverage
- Develop instruction-level stimulus and compare results against a golden instruction set simulator
- Verify memory ordering coherence exceptions and privilege behavior
- Verify latency bandwidth and cache behavior under representative workloads
- Execute regressions and track bug and coverage metrics
- Support emulation FPGA prototyping and pre-silicon software bring-up and drive root-cause analysis
Requirements
- 8 or more years verifying high-performance CPUs or complex digital designs
- Have strong computer architecture and microarchitecture fundamentals
- Have experience with SystemVerilog UVM C C++ assertions and coverage-driven verification
- Own design verification from test planning through coverage closure
- Have experience writing test plans portable testbenches and transactors
- Have experience debugging issues across hardware and software boundaries
- Hold a BS or higher in Computer Engineering Electrical Engineering or Computer Science
- Work effectively in a collaborative multidisciplinary engineering environment
- Knowledge of ARM or RISC-V instruction sets cache coherence memory ordering prefetching branch prediction speculative execution or address translation is preferred
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements