Design Verification Engineer
Summary
Design Verification Engineer verifying complex internal IP blocks (compute engines, accelerators, custom logic) within SoC environments using UVM-based verification, 5 days onsite in San Jose.
Position: Design Verification Engineer Type/Duration: Full time//Permanent Location: San Jose, CA (5 Days onsite in a week) Summary: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Key Responsibilities: Develop and maintain UVM-based verification environments Create test plans, testcases, and coverage models Perform functional verification of RTL designs Debug RTL and testbench issues Drive coverag…
