Design Verification Engineer– Penang, Malaysia

Responsibilities:

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC and AI-SOC products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 2-3 years of experience at block/sub-system/full-chip verfication level.
• Proficiency in SystemVerilog, C/C++, Python, Makefile, with a strong understanding of digital design principles.
• AMBA Protocol, and such as APB, AHB, AXI or ACE or CHI.
• Any of high speed IO, such as PCIe, USB, SATA, Ethernet, MIPI and so on.
• Any of memory system, such as DDR, UFS, SD or EMMC and so on.
• Familiar with CPU/DSP bootup flow, and GCC toolchain.
• Familiar with C-SV DPI development based on any of simulator.
• Nice to have NPU bootup flow, and related toolchain development experience.
• Low power verification experience is better.
• Knowledge of low-power design techniques and verification methodologies is a plus.