Design Verification Engineer
This position is no longer accepting applications (closed Oct 25, 2026).
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Description
We are seeking a Senior Formal Verification Engineer with 8–10 years of experience in semiconductor design verification and a strong focus on formal verification methodologies. The ideal candidate will have hands-on experience with Synopsys VC Formal and/or Cadence JasperGold, strong expertise in SystemVerilog Assertions (SVA) and formal property specification, and experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis. The candidate shoul…