Design Verification Engineer
Posted Updated
Summary
Design Verification Engineer at Velaura AI in Bangalore developing verification strategies and environments for complex SoC hardware: building SystemVerilog/UVM and C/C++ testbenches, verifying compute engines, memory subsystems, and interconnects, and supporting emulation, FPGA prototyping, and post-silicon debug.
You will develop verification strategies and environments for complex SoC hardware. You will verify system behavior, performance, reliability, and safety across RTL blocks and hardware/software systems, investigate bugs, and support emulation, FPGA prototyping, and post-silicon debug.
Responsibilities
- Develop and execute verification strategies for SoC components
- Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, and emulation
- Define verification plans, coverage goals, and correctness criteria with architects and RTL engineers
- Verify compute engines, memory subsystems, interconnects, processors, DMA engines, and SoC infrastructure
- Perform hardware/software co-verification
- Verify performance, latency, bandwidth, QoS, and real-time behavior
- Develop assertions, checkers, scoreboards, and automated verification infrastructure
- Participate in emulation, FPGA prototyping, and pre-silicon software bring-up
- Investigate bugs and perform root-cause analysis across hardware and software
- Perform post-silicon debug and root-cause analysis
Requirements
- Experience verifying complex digital systems
- Computer architecture, microarchitecture, SoC architecture, and digital design knowledge
- SystemVerilog
- UVM
- C/C++
- Assertions
- Coverage-driven verification
- Formal verification
- Memory systems
- Interconnect fabrics
- Caches
- DMA engines
- Processors or accelerator architectures
- System-level debugging
Benefits
- Competitive equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements