DFT Engineer Architect Manager or Senior Manager

You will define and lead Design-for-Test architecture, strategy, methodology, and execution for complex AI and high-performance computing ASIC and SoC designs. You will oversee DFT implementation from RTL integration through verification, pattern generation, sign-off, silicon bring-up, yield ramp, and production testing. You will collaborate with design, verification, physical design, timing, validation, product engineering, and manufacturing functions; improve DFT flows and automation; resolve implementation issues; establish quality targets; and mentor DFT engineers.

Responsibilities

• Define and drive DFT architecture, strategy, and methodology for complex ASIC and SoC designs.
• Lead planning and implementation of scan insertion, compression, ATPG, MBIST, LBIST, boundary scan, JTAG, IJTAG, test access mechanisms, and fault simulation.
• Own end-to-end DFT execution from architecture definition through production ramp.
• Collaborate with cross-functional engineering and manufacturing functions to integrate DFT requirements.
• Develop test plans that optimize fault coverage, test cost, test quality, and manufacturability.
• Drive ATPG pattern generation, coverage analysis, fault grading, diagnosis, and pattern validation.
• Define and implement memory test strategies, including MBIST, repair analysis, redundancy handling, and memory test integration.
• Lead DFT verification, including simulation, formal verification, connectivity checks, test-mode validation, and pattern verification.
• Resolve DFT-related timing, congestion, test-mode constraints, scan reordering, and implementation closure challenges.
• Support post-silicon debug, yield analysis, failure diagnosis, production test correlation, and field failure analysis.
• Establish DFT quality metrics, sign-off criteria, coverage targets, and execution checkpoints.
• Improve DFT tools, flows, automation, and methodologies.
• Lead and mentor DFT engineers.

Requirements

• 15+ years of experience in DFT architecture, implementation, and sign-off for ASIC or SoC designs.
• Experience defining and leading DFT strategy for large-scale ASIC or SoC programs through silicon production.
• Expertise in scan design, scan compression, ATPG, MBIST, LBIST, JTAG, boundary scan, IJTAG, test access architecture, and fault simulation.
• Experience with ATPG pattern generation, coverage closure, pattern validation, diagnosis, and silicon correlation.
• Experience leading DFT teams and cross-functional execution across multiple projects or design programs.
• Experience with post-silicon debug, yield improvement, failure diagnosis, production test support, and field failure analysis.
• Understanding of DFT impact on RTL design, physical design, timing closure, low-power implementation, and sign-off.
• Experience with industry-standard DFT and EDA tools.
• Familiarity with advanced fault models, at-speed testing, transition delay testing, stuck-at testing, path delay testing, cell-aware test, and timing-aware ATPG.

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements