Physical Design Engineer

You will drive the physical implementation and sign-off of critical high-performance silicon blocks from RTL to GDSII. You will optimize synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure, extraction, physical verification, and power integrity. You will resolve complex design-closure issues, improve implementation methodologies and automation flows, collaborate across engineering functions, and provide technical leadership and mentoring.

Responsibilities

• Own critical design blocks from RTL to GDSII through synthesis, floorplanning, place and route, timing closure, and sign-off.
• Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure.
• Drive timing convergence across multiple modes and corners while meeting frequency, power, area, and schedule goals.
• Evaluate micro-architecture feasibility and timing, power, congestion, and area tradeoffs with RTL and architecture teams.
• Develop physical design methodologies, implementation recipes, and automation flows.
• Perform logic synthesis, placement optimization, CTS, routing, timing ECOs, physical ECOs, extraction, and final sign-off.
• Analyze and resolve timing, congestion, clocking, signal integrity, power integrity, and physical verification issues.
• Perform DRC, LVS, ERC, antenna, density, metal fill, and layout-quality checks.
• Drive EM/IR analysis and ensure power-delivery and sign-off readiness.
• Use industry-standard implementation and sign-off tools.
• Create and maintain Tcl, Perl, and Python scripts to automate physical design tasks.
• Collaborate with RTL, DFT, STA, verification, CAD, packaging, and product engineering functions.
• Provide technical leadership in physical design closure and advanced-node implementation.
• Mentor engineers and establish physical design best practices.

Requirements

• 8+ years of hands-on experience in physical design implementation and sign-off for complex semiconductor designs.
• Experience delivering high-performance blocks from RTL to GDSII in advanced technology nodes.
• Experience closing high-performance compute-intensive IP blocks.
• Knowledge of synthesis, floorplanning, placement, CTS, routing, extraction, timing closure, and physical sign-off.
• Expertise in static timing analysis, timing constraints, clocking methodologies, multi-corner multi-mode closure, and timing ECOs.
• Experience with Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, and Apache RedHawk.
• Experience with advanced process technologies, preferably sub-5nm nodes.
• Knowledge of power planning, IR drop, electromigration, signal integrity, congestion analysis, and physical design quality checks.
• Scripting skills in Tcl, Perl, or Python.
• Ability to work across multiple projects and geographically distributed teams.

Benefits

• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements