DFT Engineer

1.Development and implementation for advanced at speed testing and DFT, JTAG, MBIST, SCAN Chain and ATPG.
2.Requirement:
2-1. BS or MS degree in EE or related.
2-2. Familiar with DFT related flow and EDA tools
2-3. Experience in Logic simulation flow (e.g. Cadence NCVerilog or Synopsys VCS).
2-4. Experience in chip design flow and chip implementation flow is a plus.
2-5. Proficient in Tcl and Unix shell.
2-6. Team work and Proactive attitude.

【共創A+聯詠】
穩健踏實、專家精神、創造優勢
驅動科技、開發創新、引領未來
邀請優秀人才，共創A+聯詠