Formal Verification Framework for Hardware IPs Validation
Summary
A design verification role (internship-style, 6+ months) at Apple's London design center, building a formal verification framework for hardware IPs: defining property sets, writing SVA, executing formal proofs, and documenting verification methodology across Apple's chip platforms.
Join a rapidly growing team at our London design center. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The AMS IP team owns a wide portfolio of IPs & complete subsystems going to all the Apple products. In this context the Design Verification Engineer will have to interface with many different teams at Apple and build knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, defining the verification strategy & plan, executing the verification, doing performance analysis and handling all the different quality metrics to signoff the verification.
Define comprehensive property sets for functional coverage of hardware models Formalize verification properties using SVA Execute formal proofs and analyze convergence behavior (accuracy VS execution time) Document methodology and best practices for the verification flow
Minimum Qualifications
- Currently enrolled in Computer Science or equivalent
- Knowledge of formal verification techniques
- Knowledge of Verilog and/or VHDL
- Passionate about mathematics, and good mathematical/analytical sense
- Scripting language knowledge (perl/python)
- Good written and verbal communication skills
- Experience in working with international teams
Preferred Qualifications
- Master's / Bachelor's in Computer Science or equivalent
- You are available for 6 months or more