IC Design Engineer
Summary
R&D engineer responsible for physical design and implementation of high-performance System-On-Chip ASICs (500M–800M gates) at 5nm/3nm/2nm nodes using commercial and in-house EDA tools, collaborating with RTL teams and supporting customers.
1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key competencies required are:
- Working experience leading team in physical design implementation of large ASICs (500 to 800 million gates complexity).
- Demonstrated ability in providing technical support to customers and managing customer working relationship.
- Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
- In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
- Collaborating with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.
2. Utilize commercial and in-house EDA tools for the design and implementation of 500 ~ 800 million gate integrated circuits in 5nm/3nm/2nm process technologies.
3. Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products
Qualifications: Requirements
1. Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 7 years or more experience in a relevant field.
2. Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
3. Strong analytical problem-solving skills and the ability to collaborate in cross-functional team environments
4. Experience in Perl, Tcl & Python Scripting languages