interconnect fabric design and system level cache IP engineer

1. Interconnect IP/Fabric IP/System-level-cache IP/related bus-subsys design for different products (smartphone/AUTO/...)
2. Cowork with DV team to secure functionality
3. Cowork with performance validation team to secure performance requirement (BW/latency) is met
4. IP Design Quality Control flow execution (lint, CDC, spyglass DFT, UPF,...)
5. RTL Front-End flow execution (SDC quality check, clock constraint check, ...)

#LI-LL1