Junior Design Verification Engineer, Amazon Leo
Posted Updated
Description
Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
The Role:
Be part of Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
In this role you will:
· Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
· Participate in the validation of ASIC implementations in Verilog/SystemVerilog
· Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
· Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
The Role:
Be part of Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
In this role you will:
· Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
· Participate in the validation of ASIC implementations in Verilog/SystemVerilog
· Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
· Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.