Memory IP Design engineer
Posted Updated
Description
1. Customizate SRAM IP design for Phison Project.
2. Memory/SRAM circuit simulation and design verification.
3. Familiar with Tcl coding for SRAM compiler tiling engine.
4. Memory/SRAM yield improvement & test IP development.
5. SRAM liberty characterization flow.
6. Familier with 6T cell Bit cell Write and Read margin.
7. Memory IP FE model, tmax, tessent ,RTL, LEF，verilog model.
8. SRAM macro EMIR evaluation .