Physical ASIC Design Implementation Engineer

Join our innovative team as a Physical ASIC Design Implementation Engineer, where you'll work on cutting-edge projects spanning a range of technologies from N2 to 180nm. Leverage your expertise in the full backend process, from netlist to GDSII-out, and become an integral part of advancing our client’s technological capabilities.

About the role

As a Physical ASIC Design Implementation Engineer, you will be involved in a dynamic environment working on top-level chips and block-level designs. You will be responsible for managing direct communication with clients, tailoring solutions to their specifications, and ensuring seamless execution throughout the design cycle with full Cadence Innovus Place&Route flow understanding. Your role will involve partitioning tasks, driving signoff closure, and leading technical discussions.

Key responsibilities

• Liaise with customers for future project specifications and execution

• Demonstrate full proficiency in Cadence Innovus Place&Route flow

• Lead partitioning and division of the top-level SDC file into timing constraints for sub-blocks

• Collaborate with the Physical Design implementation team for signoff closure.

• Manage technical communication with customers regarding their specifications

• Set up flows for specific library sets and foundry nodes

• Develop low power designs (UPF) and debug SDC files

• Expertise in Floorplanning & power grid

• design for top-level and block-level tasks

• Conduct Placement, CTS & Routing, and solve setup & hold violations

• Execute sign-off extraction, timing, and power analysis

• Perform physical verification, equivalence checks, and more

What we're looking for

• We seek a skilled professional with a strong background in physical ASIC design implementation and experience in Cadence Innovus Place&Route flow

• Excellent understanding of chip design from netlist to GDSII-out

• Proven ability in partitioning and dividing top-level data into sub-block constraints

• Experience with low power design and SDC file debugging

• Familiarity with various verification methods and sign-off processes

Why join us?

At VeroTech, we empower engineers to grow, innovate, and lead. Join a dynamic community where you’ll work on cutting-edge R&D projects, receive personalized career development, and thrive in a supportive, inclusive culture. Enjoy flexibility with remote work options, a competitive salary package, and additional benefits like meal vouchers, insurance, and a company car. Be part of impactful projects that shape the future of technology while maintaining a healthy work-life balance.

Ready to inspire?

Apply now and take the next step in your career. Let’s build the future together!