Physical Design Engineer - Frontend

You will implement RTL-to-GDS physical-design flows and optimize power, performance, and area. You will perform logic synthesis, clock-gating insertion, equivalence checking, functional ECO, static timing analysis, simulation, timing signoff, power estimation, PVT adjustments, and quality-of-results analysis. You will also support design service providers and contractors.

Responsibilities

• Implement RTL-to-GDS physical-design processes to optimize power, performance, and area
• Conduct logic synthesis, clock-gating insertion, and architecture feasibility checks
• Check logic equivalence and perform functional ECO
• Perform static timing analysis and simulation to optimize logic and overall design
• Manage setup and hold timing signoff and logic design-rule fixes
• Estimate power consumption and optimize PPA, including PVT adjustments
• Propose architectural changes to improve design quality of results
• Support design service providers and contractors to meet turnaround-time requirements

Requirements

• At least 8 years of semiconductor-industry experience with EDA tool workflows
• Proficiency in Tcl, Perl, or Python for workflow automation and data visualization
• Extensive experience with physical-design processes and RTL-to-GDS automation tools
• Understanding of in-place optimization during ECO
• Experience leading one or more aspects of physical implementation
• Experience extracting design parameters, summarizing quality of results, and analyzing trends to improve quality of results