Physical Design Engineer (Fusion Compiler)
We are looking for experienced Physical Design Engineers with 7–8 years of proven professional experience to join our IP Design team.
As a Physical Design Engineer, you will be part of a highly competent team supporting implementation and timing closure for advanced ASIC and IP designs. You will apply strong synthesis, static timing analysis, and constraint-development expertise to deliver high-quality physical implementation results.
Your Main Responsibilities
- Execute ASIC synthesis and physical design flows using Synopsys Fusion Compiler and PrimeTime.
- Perform static timing analysis, timing closure, and PTC activities across implementation milestones.
- Develop, validate, and maintain SDC constraints for accurate and robust timing analysis.
- Analyze timing, constraint, and implementation issues; collaborate with design and relevant teams to drive closure.
- Support implementation sign-off deliverables and maintain clear documentation of analyses and results.
Benefits
- 7–8 years of relevant ASIC physical design experience.
- Strong understanding of ASIC design and synthesis fundamentals.
- Hands-on experience with Synopsys Fusion Compiler and PrimeTime flows (or equivalent flows).
- Strong experience in STA, timing closure, and PTC.
- Experience in SDC constraint development and validation.
- Access to and practical experience with foundry data from TSMC, Intel, and/or Samsung.