Physical Design Engineer (工作地點:新竹)

Role Summary

• Physical Design Engineer to own and execute block-level or top-level netlist-to-GDSII implementation, optimizing PPA (Power, Performance, Area) and ensuring timing convergence for the next-generation silicon.

Key Responsibilities

• Execution: Perform chip floorplanning, placement, clock tree synthesis (CTS), and detailed routing (PNR) using industry-leading EDA flows.
• Sign-off & Verification: Drive Static Timing Analysis (STA), timing constraints setup, Logic Equivalency Checking (LEC), low-power verification (VCLP), and EMIR analysis to ensure structural integrity.

Requirements & Qualifications

• 2+ years of hands-on experience in ASIC physical design (PNR, STA, and physical verification closure).
• Proficiency with standard EDA tools (e.g., Synopsys Fusion Compiler/PrimeTime or Cadence Innovus) and scripting languages (Tcl, Python, or Perl).
• Strong understanding of deep sub-micron process nodes and low-power design methodologies (UPF/CPF).