NewBe an early applicant

12 hr. ago 10 hr. ago

Physical Design Lead

Apply

12 hr. ago 10 hr. ago

Discussion

Enthrive Techworld Solutions Physical Design Lead

Apply

Discussion

Strong expertise in ASIC implementation and advanced technology nodes (7nm/5nm/3nm preferred)
ICC2 / Fusion Compiler or Cadence Innovus
PrimeTime or Tempus
Calibre / ICV / Pegasus
RedHawk or Voltus
Proficiency in TCL, Python, Perl, and Make

Skills

What Lead Design jobs ask for — and how much of it you have →

Apply

SignOff Semiconductors

22 hours ago

Lead Physical Design Engineer

APACLead

India

Lead a physical design team taking high-performance SoCs from RTL to GDSII at SignOff Semiconductors in Bangalore: floorplanning, CTS, routing, MMMC timing closure, power intent (UPF/CPF) and EM/IR checks, and DRC/LVS sign-off, using Synopsys/Cadence flows (ICC2, Fusion Compiler, Innovus, PrimeTime) plus TCL/Python/Perl flow automation.

AI Automation GPU Machine Learning Perl +3 skills

Nokia

4 days ago

SoC Physical Design Engineer

HybridEuropeFull-time H-1B sponsor history

Italy

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for…

Automation Perl Python Tcl

Astera Labs

last week

Teach Lead Physical Design Engineer

APACLead H-1B sponsor history Canada LMIA employer

Singapore

Lead physical design engineer at Astera Labs in Singapore implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes. Day-to-day covers floorplanning, placement, CTS, routing, EM/IR and signoff (DRC/LVS/ERC) using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills

Cisco

4 weeks ago

ASIC Physical Design Engineer II (Full Time) - United States

North AmericaFull-timeMiddle Licensed NL sponsor

United States

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a…

AI Asic Automation Cisco Networking +3 skills

Efficient Computer

last month

Physical Design - SOC Top Lead

North AmericaLead

United States

Lead the physical design and tapeout of energy-efficient AI/ML SoCs, integrating blocks, timing, power, and signal integrity to deliver GDS-ready chips using advanced finfet nodes.

AI Bash JTAG Python Signal Integrity +1 skills

200K – 250K $

Astera Labs

last week

Principal Physical Design Engineer

APACPrincipal H-1B sponsor history Canada LMIA employer

Singapore

Physical design engineer at Astera Labs implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes: floorplanning, placement, CTS, routing, EM/IR and congestion analysis, ECOs, and DRC/LVS/ERC signoff using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills

Description

Skills

Lead Physical Design Engineer

SoC Physical Design Engineer

Teach Lead Physical Design Engineer

ASIC Physical Design Engineer II (Full Time) - United States

Physical Design - SOC Top Lead

Principal Physical Design Engineer

See also